View M58BW032DT60T6T_989533.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M58BW032BT, M58BW032BB M58BW032DT, M58BW032DB
32 Mbit (1Mb x32, Boot Block, Burst) 3.3V Supply Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
SUPPLY VOLTAGE - VDD = 3.0V to 3.6V for Program, Erase and Read - VDDQ = VDDQIN = 1.6V to 3.6V for I/O Buffers HIGH PERFORMANCE - Access Time: 45, 55 and 60ns - 75MHz Effective Zero Wait-State Burst Read - Synchronous Burst Reads - Asynchronous Page Reads MEMORY ORGANIZATION - Eight 64 Kbit small parameter Blocks - Four 128Kbit large parameter Blocks (of which one is OTP) - Sixty-two 512Kbit main Blocks
Figure 1. Packages
PQFP80 (T)
BGA

HARDWARE BLOCK PROTECTION - WP pin Lock Program and Erase - VPEN signal for Program/Erase Enable SOFTWARE BLOCK PROTECTION - Tuning Protection to Lock Program and Erase with 64-bit User Programmable Password (M58BW032B version only) SECURITY - 64-bit Unique Device Identifier (UID) FAST PROGRAMMING - Write to Buffer and Program capability OPTIMIZED FOR FDI DRIVERS - Common Flash Interface (CFI) - Fast Program/Erase Suspend feature in each block LOW POWER CONSUMPTION - 100A Typical Standby
LBGA80 (ZA) 10 x 8 ball array
ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Top Device Code M58BW032xT: 8838h - Bottom Device Code M58BW032xB: 8837h OPERATING TEMPERATURE RANGE - Automotive (Grade 3): -40 to 125C - Industrial (Grade 6): -40 to 90C
November 2004
1/60
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. LBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. PQFP Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Tuning Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2. Top Boot Block Addresses, M58BW032BT, M58BW032DT . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Bottom Boot Block Addresses, M58BW032BB, M58BW032DB . . . . . . . . . . . . . . . . . . . 12 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Inputs/Outputs (DQ0-DQ31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Disable (GD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Program/Erase Enable (VPEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Burst Clock (K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Burst Address Advance (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output Supply Voltage (VDDQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input Supply Voltage (VDDQIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ground (VSS and VSSQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Don't Use (DU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Not Connected (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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Reset/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Synchronous Burst Read Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Standby Disable Bit (M14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 X-Latency Bits (M13-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Y-Latency Bit (M9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Wrap Burst Bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 5. Example Burst Configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Erase All Main Blocks Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Write to Buffer and Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Tuning Protection Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Tuning Protection Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Set Block Protection Configuration Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Clear Block Protection Configuration Register Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 8. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 9. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 10. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 27 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Program/ Write to Buffer and Program/Tuning Protection Unlock Status (Bit 4) . . . . . . . . . . 28 VPEN Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Tuning Protection Status (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 13. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 6. AC Measurement Input Output Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 14. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8. Asynchronous Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 16. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 9. Asynchronous Latch Controlled Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . 34 Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . . 34 Figure 10.Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 18. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 11.Asynchronous Write AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 12.Asynchronous Latch Controlled Write AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics . . . . . . . . . . . . . . . 38 Figure 13.Synchronous Burst Read (Data Valid from 'n' Clock Rising Edge) . . . . . . . . . . . . . . . . . 39 Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 14.Synchronous Burst Read (Data Valid from 'n' Clock Rising Edge) . . . . . . . . . . . . . . . . . 40 Figure 15.Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . . 41 Figure 16.Synchronous Burst Read - Burst Address Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 17.Reset, Power-Down and Power-up AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 21. Reset, Power-Down and Power-up AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 42 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 18.LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline . . . . . . 43 Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical Data . . . . . . . . . 43 Figure 19.PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline . . . . . . . . . . . . . . . . . . . . . 44 Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data. . . . . . . . . . . . . . 44 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 APPENDIX A.FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 20.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 21.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 47 Figure 22.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 23.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 24.Unlock Device and Change Tuning Protection Code Flowchart . . . . . . . . . . . . . . . . . . . 50
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Figure 25.Unlock Device and Program a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . 51 Figure 26.Unlock Device and Erase a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . . . 52 Figure 27.Power-up Sequence to Burst the Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 28.Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . . 54 Figure 29.Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . . 55 Figure 30.Command Interface and Program Erase Controller Flowchart (c) . . . . . . . . . . . . . . . . . 56 Figure 31.Command Interface and Program Erase Controller Flowchart (d) . . . . . . . . . . . . . . . . . 57 Figure 32.Command Interface and Program Erase Controller Flowchart (e) . . . . . . . . . . . . . . . . . 58 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 25. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
SUMMARY DESCRIPTION
The M58BW032B/D is a 32Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a DoubleWord basis using a 3.0V to 3.6V VDD supply for the circuit and a VDDQ supply down to 1.6V for the Input and Output buffers. The devices support Asynchronous (Latch Controlled and Page Read) and Synchronous Bus operations. The Synchronous Burst Read Interface allows a high data transfer rate controlled by the Burst Clock, K, signal. It is capable of bursting fixed or unlimited lengths of data. The burst type, latency and length are configurable and can be easily adapted to a large variety of system clock frequencies and microprocessors. All Writes are Asynchronous. On power-up the memory defaults to Read mode with an Asynchronous Bus. The device features an asymmetrical block architecture. The M58BW032B/D has an array of 62 main blocks of 512 Kbits each, plus 4 large parameter blocks of 128Kbits each and 8 small parameter blocks of 64 Kbits each. The large and small parameter blocks are located either at the top (M58BW032BT, M58BW032DT) or at the bottom (M58BW032BB, M58BW032DB) of the address space. The first large parameter block is referred to as Boot Block and can be used either to store a boot code or parameters. The memory array organization is detailed in Tables 2, Top Boot Block Addresses and 3, Bottom Boot Block Addresses. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. Erase can be suspended in order to perform either Read or Program in any other block and then resumed. Program can be suspended to Read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. All blocks are protected during power-up. The M58BW032B features four different levels of hardware and software block protection to avoid unwanted program/erase operations: Write/Protect Enable input, WP, provides a hardware protection of a combination of blocks from program or erase operations. The Block Protection configuration can be defined individually by issuing a Set Block Protection Configuration Register or Clear Block Protection Configuration Register commands. All Program or Erase operations are blocked when Reset, RP, is held low. A Program/Erase Enable input, VPEN, is used to protect all blocks, preventing Program and Erase operations from affecting their data. The Program and Erase commands can be password protected by the Tuning Protection command. The M58BW032D offers the same protection features with the exception of the Tuning Block Protection which is disabled in the factory. A Reset/Power-down mode is entered when the RP input is Low. In this mode the power consumption is reduced to the standby level, the device is write protected and both the Status and Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High. A manufacturer and device code are available. They can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the memory. Finally, the M58BW032B/D features a Unique Device Identifier (UID) which is programmed by ST. It is unique for each die and can be used to implement cryptographic algorithms to improve security. The memory is offered in PQFP80 (14 x 20mm) and LBGA80 (1.0mm pitch) packages and it is supplied with all the bits erased (set to '1').
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Figure 2. Logic Diagram Table 1. Signal Names
A0-A19 DQ0-DQ7 Address inputs Data Input/Output, Command Input Data Input/Output, Burst Configuration Register Data Input/Output Burst Address Advance Chip Enable Output Enable Burst Clock Latch Enable Valid Data Ready Reset /Power-Down Write Enable Output Disable Write Protect Supply Voltage Power Supply for Output Buffers Power Supply for Input Buffers only Program/Erase Enable Ground Input/Output Ground Not Connected Internally Don't Use as Internally Connected
VDD VDDQ VDDQIN VPEN
DQ8-DQ15 DQ16-DQ31
A0-A19 K L E RP G GD W WP B M58BW032BT M58BW032BB M58BW032DT M58BW032DB
B
DQ0-DQ31
E G K L
R
R RP W GD WP VDD VDDQ VDDQIN
VSS
VSSQ
AI08918b
VPEN VSS VSSQ NC DU
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 3. LBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A15
A14
VDD
VPEN
VSS
A6
A3
A2
B
A16
A13
A12
A9
A8
A5
A4
A1
C
A17
A18
A11
A10
NC
A7
DU
A0
D
DQ3
DQ0
A19
DU
NC
DQ31
DQ30
DQ29
E
VDDQ
DQ4
DQ2
DQ1
DQ27
DQ28
DQ26
VDDQ
F
VSSQ
DQ7
DQ6
DQ5
NC
DQ25
DQ24
VSSQ
G
VDDQ
DQ8
DQ10
DQ9
DQ22
DQ21
DQ23
VDDQ
H
DQ13
DQ12
DQ11
WP
DQ17
DQ19
DQ18
DQ20
J
DQ15
DQ14
L
B
E
G
R
DQ16
K
VDDQIN
RP
K
VSS
VDD
W
GD
DU
AI08920b
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 4. PQFP Connections (Top view through package)
DU R GD WP W G E VDD B VSS L NC NC K RP VDDQIN 80 73 65
25
32
VSS VPEN VDD A9 A10 A11 A12 A13 A14 A15
A3 A4 A5 A6 A7 A8
40
DQ16 DQ17 DQ18 DQ19 VDDQ VSSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 VDDQ VSSQ DQ28 DQ29 DQ30 DQ31 DU A0 A1 A2
1
64
12
M58BW032BT M58BW032BB M58BW032DT M58BW032DB
53
24
41
DQ15 DQ14 DQ13 DQ12 VSSQ VDDQ DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 VSSQ VDDQ DQ3 DQ2 DQ1 DQ0 A19 A18 A17 A16
AI08919c
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Block Protection The M58BW032B features four different levels of block protection. The M58BW032D has the same block protection with the exception of the Tuning Block Protection, which is disabled in the factory. Write Protect Pin, WP, - When WP is Low, VIL, the protection status that has been configured in the Block Protection Configuration Register is activated. The Block Protection Configuration Register is volatile. Any combination of blocks is possible. Any attempt to program or erase a protected block will be ignored and will return an error in the Status Register (see Table 11., Status Register Bits). Reset/Power-Down Pin, RP, - If the device is held in reset mode (RP at VIL), no program or erase operations can be performed on any block. Program/Erase Enable, VPEN, - VPEN protects all blocks preventing Program and Erase operations from affecting their data. Program/Erase Enable must be kept High (VIH) during all Program/Erase Controller operations, otherwise the operations is not guaranteed to succeed and data may become corrupt. Tuning Block Protection - M58BW032B features a 64 bit password protection for program and erase operations for a fixed number of blocks After power-up or reset the device is tuning protected. An Unlock command is provided to allow program or erase operations in all the blocks. After a device reset the first two kinds of block protection (WP, RP) can be combined to give a flexible block protection. They do not affect the Tuning Block Protection. When the two protections are disabled, WP and RP at VIH, the blocks locked by the Tuning Block Protection cannot be modified. All blocks are protected at power-up. Tuning Block Protection The Tuning Block Protection is a software feature to protect blocks from program or erase operations. It allows the user to lock program and erase operations with a user definable 64 bit code. It is only available on the M58BW032B version. The code is written once in the Tuning Protection Register and cannot be erased. When shipped the flash memory will have the Tuning Protection Code bits set to `1'. The user can program a `0' in any of the 64 positions. Once programmed it is not possible to reset a bit to `1' as the cells cannot be erased. The Tuning Protection Register can be programmed at any moment (after providing the correct code), however once all bits are set to `0' the Tuning Protection Code can no longer be altered. The Tuning Protection Code locks the program and erase operations of all the blocks except for blocks 12 and 13 for the bottom configuration, and blocks 60 and 61 for the top configuration. The tuning blocks are "locked" if the tuning protection code has not been provided, and "unlocked" once the correct code has been provided. The tuning blocks are locked after reset or power-up. The tuning protection status can be monitored in the Status Register. Refer to the Status Register section. Refer to the Command Interface section for the Tuning Protection Block Unlock and Tuning Protection Program commands. See Appendix A, Figure 24, 25 and 26 for suggested flowcharts for using the Tuning Block Protection commands.
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Table 2. Top Boot Block Addresses, M58BW032BT, M58BW032DT
# 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 Size (Kbit) 128 128 128 128 64 64 64 64 64 64 64 64 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 Address Range(1) FF000h-FFFFh FE000h-FEFFFh(3) FD000h-FDFFFh FC000h-FCFFFh FB800h-FBFFFh FB000h-FB7FFh FA800h-FAFFFh FA000h-FA7FFh F9800h-F9FFFh F9000h-F97FFh F8800h-F8FFFh F8000h-F87FFh F4000h-F7FFFh F0000h-F3FFFh EC000h-EFFFFh E8000h-EBFFFh E4000h-E7FFFh E0000h-E3FFFh DC000h-DFFFFh D8000h-DBFFFh D4000h-D7FFFh D0000h-D3FFFh CC000h-CFFFFh C8000h-CBFFFh C4000h-C7FFFh C0000h-C3FFFh BC000h-BFFFFh B8000h-BBFFFh B4000h-B7FFFh B0000h-B3FFFh AC000h-AFFFFh A8000h-ABFFFh A4000h-A7FFFh A0000h-A3FFFh 9C000h-9FFFFh 98000h-9BFFFh 94000h-97FFFh TP(2) yes yes yes yes yes yes yes yes yes yes yes yes no no yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes # 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size (Kbit) 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 Address Range(1) 90000h-93FFFh 8C000h-8FFFFh 88000h-8BFFFh 84000h-87FFFh 80000h-83FFFh 7C000h-7FFFFh 78000h-7BFFFh 74000h-77FFFh 70000h-73FFFh 6C000h-6FFFFh 68000h-6BFFFh 64000h-67FFFh 60000h-63FFFh 5C000h-53FFFFh 58000h-5BFFFh 54000h-57FFFh 50000h-53FFFh 4C000h-4FFFFh 48000h-4BFFFh 44000h-47FFFh 40000h-43FFFh 3C000h-3FFFFh 38000h-3BFFFh 34000h-37FFFh 30000h-33FFFh 2C000h-2FFFFh 28000h-2BFFFh 24000h-27FFFh 20000h-23FFFh 1C000h-1FFFFh 18000h-1BFFFh 14000h-17FFFh 10000h-13FFFh 0C000h-0FFFFh 08000h-0BFFFh 04000h-07FFFh 00000h-03FFFh TP(2) yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes
Note: 1. Addresses are indicated in 32-bit addressing. 2. TP = Tuning Protected Block, only available for the M58BW032B. 3. OTP Block.
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Table 3. Bottom Boot Block Addresses, M58BW032BB, M58BW032DB
# 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 Size (Kbit) 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 Address Range(1) FC000h-FFFFFh F8000h-FBFFFh F4000h-F7FFFh F0000h-F3FFFh EC000h-EFFFFh E8000h-EBFFFh E4000h-E7FFFh E0000h-E3FFFh DC000h-DFFFFh D8000h-DBFFFh D4000h-D7FFFh D0000h-D3FFFh CC000h-CFFFFh C8000h-CBFFFh C4000h-C7FFFh C0000h-C3FFFh BC000h-BFFFFh B8000h-BBFFFh B4000h-B7FFFh B0000h-B3FFFh AC000h-AFFFFh A8000h-ABFFFh A4000h-A7FFFh A0000h-A3FFFh 9C000h-9FFFFh 98000h-9BFFFh 94000h-97FFFh 90000h-93FFFh 8C000h-8FFFFh 88000h-8BFFFh 84000h-87FFFh 80000h-83FFFh 7C000h-7FFFFh 78000h-7BFFFh 74000h-77FFFh 70000h-73FFFh 6C000h-6FFFFh 68000h-6BFFFh TP(2) yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes # 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size (Kbit) 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 64 64 64 64 64 64 64 64 128 128 128 128 Address Range(1) 64000h-67FFFh 60000h-63FFFh 5C000h-53FFFFh 58000h-5BFFFh 54000h-57FFFh 50000h-53FFFh 4C000h-4FFFFh 48000h-4BFFFh 44000h-47FFFh 40000h-43FFFh 3C000h-3FFFFh 38000h-3BFFFh 34000h-37FFFh 30000h-33FFFh 2C000h-2FFFFh 28000h-2BFFFh 24000h-27FFFh 20000h-23FFFh 1C000h-1FFFFh 18000h-1BFFFh 14000h-17FFFh 10000h-13FFFh 0C000h-0FFFFh 08000h-0BFFFh 07800h-07FFFh 07000h-077FFh 06800h-06FFFh 06000h-067FFh 05800h-05FFFh 05000h-057FFh 04800h-04FFFh 04000h-047FFh 03000h-03FFFh 02000h-02FFFh 01000h-01FFFh(3) 00000h-00FFFh TP(2) yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes no no yes yes yes yes yes yes yes yes yes yes yes yes
Note: 1. Addresses are indicated in 32-bit Word addressing. 2. TP = Tuning Protected Block, only available for the M58BW032B. 3. OTP Block.
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A19). The Address Inputs are used to select the cells to access in the memory array during Bus Read operations either to read or to program data to. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Chip Enable must be Low when selecting the addresses. The address inputs are latched on the rising edge of Latch Enable L or Burst Clock K, whichever occurs first, in a read operation.The address inputs are latched on the rising edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a Write operation. The address latch is transparent when Latch Enable is Low, VIL. The address is internally latched in an Erase or Program operation. Data Inputs/Outputs (DQ0-DQ31). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation, or are used to input the data during a program operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. When used to input data or Write commands they are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. When Chip Enable and Output Enable are both Low, VIL, and Output Disable is at VIH, the data bus outputs data from the memory array, the Electronic Signature, the Block Protection Configuration Register, the CFI Information or the contents of Burst Configuration Register or Status Register. The data bus is high impedance when the device is deselected with Chip Enable at VIH, Output Enable at VIH, Output Disable at VIL or Reset/PowerDown at VIL. The Status Register content is output on DQ0-DQ7 and DQ8-DQ31 are at VIL. Chip Enable (E). The Chip Enable, E, input activates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable, E, at VIH deselects the memory and reduces the power consumption to the Standby level. Output Enable (G). The Output Enable, G, gates the outputs through the data output buffers during a read operation, when Output Disable GD is at VIH. When Output Enable G is at VIH, the outputs are high impedance independently of Output Disable. Output Disable (GD). The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is at VIH, the outputs are driven by the Output Enable. When Output Disable, GD, is at VIL, the outputs are high impedance independently of Output Enable. The Output Disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin. Write Enable (W). The Write Enable, W, input controls writing to the Command Interface, Input Address and Data latches. Both addresses and data can be latched on the rising edge of Write Enable (also see Latch Enable, L). Reset/PowerReset/Power-Down (RP). The Down, RP, is used to apply a hardware reset to the memory. A hardware reset is achieved by holding Reset/Power-Down Low, VIL, for at least tPLPH. Writing is inhibited to protect data, the Command Interface and the Program/Erase Controller are reset. The Status Register information is cleared and power consumption is reduced to the standby level (IDD1). The device acts as deselected, that is the data outputs are high impedance. After Reset/Power-Down goes High, VIH, the memory will be ready for Bus Read operations after a delay of tPHEL or Bus Write operations after tPHWL. If Reset/Power-Down goes Low, VIL, during a Block Erase, a Program or a Tuning Protection Program the operation is aborted, in a time of tPLRH maximum, and data is altered and may be corrupted. During Power-up power should be applied simultaneously to VDD and VDDQ(IN) with RP held at VIL. When the supplies are stable RP is taken to VIH. Output Enable, G, Chip Enable, E, and Write Enable, W, should be held at VIH during power-up. In an application, it is recommended to associate Reset/Power-Down pin, RP, with the reset signal of the microprocessor. Otherwise, if a reset operation occurs while the memory is performing an erase or program operation, the memory may output the Status Register information instead of being initialized to the default Asynchronous Random Read. See Table 21 and Figure 17., Reset, Power-Down and Power-up AC Waveform, for more details. Program/Erase Enable (VPEN). The Program./ Erase Enable input, VPEN, protects all blocks, preventing Program and Erase operations from modifying the data. Program/Erase Enable must be kept High (VIH) during all operations when the Program/Erase Controller is active, otherwise the operation is not guaranteed to succeed and data may become corrupt. Latch Enable (L). The Bus Interface can be configured to latch the Address Inputs on the rising edge of Latch Enable, L, for Asynchronous Latch
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Enable Controlled Read or Write or Synchronous Burst Read operations. In Synchronous Burst Read operations the address is latched on the active edge of the Clock when Latch Enable is Low, VIL. Once latched, the addresses may change without affecting the address used by the memory. When Latch Enable is Low, VIL, the latch is transparent. Latch Enable, L, can remain at VIL for Asynchronous Random Read and Write operations. Burst Clock (K). The Burst Clock, K, is used to synchronize the memory with the external bus during Synchronous Burst Read operations. Bus signals are latched on the active edge of the Clock. In Synchronous Burst Read mode the address is latched on the first rising clock edge when Latch Enable is Low, VIL, or on the rising edge of Latch Enable, whichever occurs first. During Asynchronous bus operations the Clock is not used. Burst Address Advance (B). The Burst Address Advance, B, controls the advancing of the address by the internal address counter during Synchronous Burst Read operations. Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the X-latency time has expired. If Burst Address Advance is Low, VIL, the internal address counter advances. If Burst Address Advance is High, VIH, the internal address counter does not change; the same data remains on the Data Inputs/Outputs and Burst Address Advance is not sampled until the Y-latency expires. The Burst Address Advance, B, may be tied to VIL. Valid Data Ready (R). The Valid Data Ready output, R, can be used during Synchronous Burst Read operations to identify if the memory is ready to output data or not. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready, at VIH, indicates that new data is or will be available. When Valid Data Ready is Low, VIL, the previous data outputs remain active. Write Protect (WP). The Write Protect, WP, provides protection against program or erase operations. When Write Protect, WP, is at VIL, the protection status that has been configured in the Block Protection Configuration Register is activated. Program and erase operations to protected blocks are disabled. When Write Protect WP is at VIH all the blocks can be programmed or erased, if no other protection is used. Supply Voltage (VDD). The Supply Voltage, VDD, is the core power supply. All internal circuits draw their current from the VDD pin, including the Program/Erase Controller. Output Supply Voltage (VDDQ). The Output Supply Voltage, VDDQ, is the output buffer power supply for all operations (Read, Program and Erase) used for DQ0-DQ31 when used as outputs. Input Supply Voltage (VDDQIN). The Input Supply Voltage, VDDIN, is the power supply for all input signal. Input signals are: K, B, L, W, GD, G, E, A0A18 and D0-D31, when used as inputs. Ground (VSS and VSSQ). The Ground VSS is the reference for the internal supply voltage VDD. The Ground VSSQ is the reference for the output and input supplies VDDQ, and VDDQIN. It is essential to connect VSS and VSSQ together. Note: A 0.1F capacitor should be connected between the Supply Voltages, VDD, VDDQ and VDDIN and the Grounds, VSS and VSSQ to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during all operations of the parts, see Table 15., DC Characteristics, for maximum current supply requirements. Don't Use (DU). This pin should not be used as it is internally connected. Its voltage level can be between VSS and VDDQ or leave it unconnected. Not Connected (NC). This pin is not physically connected to the device.
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BUS OPERATIONS
Each bus operations that controls the memory is described in this section, see Tables 4 and 5 Bus Operations, for a summary. The bus operation is selected through the Burst Configuration Register; the bits in this register are described at the end of this section. On Power-up or after a Hardware Reset the memory defaults to Asynchronous Bus Read and Asynchronous Bus Write. No synchronous operation can be performed until the Burst Control Register has been configured. The Electronic Signature, Block Protection Configuration, CFI or Status Register will be read in asynchronous mode regardless of the Burst Control Register settings. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Asynchronous Bus Operations For asynchronous bus operations refer to Table 4 together with the following text. Asynchronous Bus Read. Asynchronous Bus Read operations read from the memory cells, or specific registers (Electronic Signature, Block Protection Configuration Register, Status Register, CFI and Burst Configuration Register) in the Command Interface. A valid bus operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable and Output Disable High, VIH. The Data Inputs/Outputs will output the value, see Figure 8., Asynchronous Bus Read AC Waveforms, and Table 16., Asynchronous Bus Read AC Characteristics., for details of when the output becomes valid. Asynchronous Read is the default read mode which the device enters on power-up or on return from Reset/Power-Down. Asynchronous Latch Controlled Bus Read. Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific registers in the Command Interface. The address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. A valid bus operation involves setting the desired address on the Address Inputs, setting Chip Enable and Latch Enable Low, VIL and keeping Write Enable High, VIH; the address is latched on the rising edge of Latch Enable. Once latched, the Address Inputs can change. Set Output Enable Low, VIL, to read the data on the Data Inputs/Outputs; see Figure Figure 9., Asynchronous Latch Controlled Bus Read AC Waveforms and Table 17., Asynchronous Latch Controlled Bus Read AC Characteristics, for details on when the output becomes valid. Note that, since the Latch Enable input is transparent when set Low, VIL, Asynchronous Bus Read operations can be performed when the memory is configured for Asynchronous Latch Enable bus operations by holding Latch Enable Low, VIL throughout the bus operation. Asynchronous Page Read. Asynchronous Page Read operations are used to read from several addresses within the same memory page. Each memory page is 4 Double-Words and is addressed by the address inputs A0 and A1. Data is read internally and stored in the Page Buffer. Valid bus operations are the same as Asynchronous Bus Read operations but with different timings. The first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. If the page changes then the normal, longer timings apply again. Page Read does not support Latched Controlled Read. See Figure 10., Asynchronous Page Read AC Waveforms, and Table 18., Asynchronous Page Read AC Characteristics, for details on when the outputs become valid. Asynchronous Bus Write. Asynchronous Bus Write operations write to the Command Interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is don't care during Bus Write operations. A valid Asynchronous Bus Write operation begins by setting the desired address on the Address Inputs, and setting Chip Enable, Write Enable and Latch Enable Low, VIL, and Output Enable High, VIH, or Output Disable Low, VIL. The Address Inputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Commands and Input Data are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole Asynchronous Bus Write operation. See Figure 11., Asynchronous Write AC Waveform, and Asynchronous Write and Latch Controlled Write AC Characteristics, for details of the timing requirements.
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Asynchronous Latch Controlled Bus Write. Asynchronous Latch Controlled Bus Write operations write to the Command Interface in order to send commands to the memory or to latch addresses and input data to program. Bus Write operations are asynchronous, the clock, K, is don't care during Bus Write operations. A valid Asynchronous Latch Controlled Bus Write operation begins by setting the desired address on the Address Inputs and pulsing Latch Enable Low, VIL. The Address Inputs are latched by the Command Interface on the rising edge of Latch Enable, Write Enable or Chip Enable, whichever occurs first. Commands and Input Data are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole Asynchronous Bus Write operation. See Figure 12., Asynchronous Latch Controlled Write AC Waveform, and Table 19., Asynchronous Write and Latch Controlled Write AC Characteristics, for details of the timing requirements. Output Disable. The data outputs are high impedance when the Output Enable, G, is at VIH or Output Disable, GD, is at VIL. Standby. When Chip Enable is High, VIH, and the Program/Erase Controller is idle, the memory enters Standby mode, the power consumption is reduced to the standby level (IDD1) and the Data Inputs/Outputs pins are placed in the high impedance state regardless of Output Enable, Write Enable or Output Disable inputs. The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst Configuration Register to `1' (see Table 15., DC Characteristics). Reset/Power-Down. The memory is in Reset/ Power-Down mode when Reset/Power-Down, RP, is at VIL. The power consumption is reduced to the standby level (IDD1) and the outputs are high impedance, independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or Write Enable, W, inputs. In this mode the device is write protected and both the Status and the Burst Configuration Registers are cleared. A recovery time is required when the RP input goes High.
Table 4. Asynchronous Bus Operations
Bus Operation Asynchronous Bus Read(2) Asynchronous Latch Controlled Bus Read Asynchronous Page Read Asynchronous Bus Write Asynchronous Latch Controlled Bus Write Output Disable, G Output Disable, GD Standby Reset/Power-Down Address Latch Write Address Latch Read Step E VIL VIL VIL VIL VIL VIL VIL VIL VIL VIH X G VIL VIH VIL VIL VIH VIH VIH VIH VIL X X GD VIH VIH VIH VIH X X X VIH VIL X X W VIH VIL VIH VIH VIL VIH VIL VIH VIH X X RP VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL L VIL VIL VIH X VIL VIL VIH X X X X A0-A19 Address Address X Address Address Address X X X X X DQ0-DQ31 Data Output High Z Data Output Data Output Data Input High Z Data Input High Z High Z High Z High Z
Note: 1. X = Don't Care 2. Data, Manufacturer Code, Device Code, Burst Configuration Register, Standby Status and Block Protection Configuration Register are read using the Asynchronous Bus Read command.
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Synchronous Bus Operations For synchronous bus operations refer to Table 5 together with the following text. Synchronous Burst Read. Synchronous Burst Read operations are used to read from the memory at specific times synchronized to an external reference clock. The valid edge of the Clock signal is the rising edge. The burst type, length and latency can be configured. The different configurations for Synchronous Burst Read operations are described in the Burst Configuration Register section. Refer to Figure 5 for examples of synchronous burst operations. In continuous burst read, one burst read operation can access the entire memory sequentially by keeping the Burst Address Advance B at VIL for the appropriate number of clock cycles. At the end of the memory address space the burst read restarts from the beginning at address 000000h. A valid Synchronous Burst Read operation begins when the Burst Clock is active and Chip Enable and Latch Enable are Low, VIL. The burst start address is latched and loaded into the internal Burst Address Counter on the valid Burst Clock K edge or on the rising edge of Latch Enable, whichever occurs first. After an initial memory latency time, the memory outputs data each clock cycle (or two clock cycles depending on the value of M9). The Burst Address Advance B input controls the memory burst output. The second burst output is on the next clock valid edge after the Burst Address Advance B has been pulled Low. Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst Controller of the microprocessor needs to insert wait states. Table 5. Synchronous Burst Read Bus Operations
Bus Operation Step Address Latch Read Synchronous Burst Read(2) Read Suspend Read Resume Burst Address Advance Read Abort, E Read Abort, RP
Note: 1. X = Don't Care, VIL or VIH. 2. M15 = 0, Bit M15 is in the Burst Configuration Register. 3. R= Rising Edge.
When Valid Data Ready is Low on the rising clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if Burst Address Advance, B, is Low. Valid Data Ready may be configured (by bit M8 of Burst Configuration Register) to be valid immediately at the rising clock edge or one data cycle before the rising clock edge. Synchronous Burst Read will be suspended if Burst Address Advance, B, goes High, VIH. If Output Enable is at VIL and Output Disable is at VIH, the last data is still valid. If Output Enable, G, is at VIH or Output Disable, GD, is at VIL, but the Burst Address Advance, B, is at VIL the internal Burst Address Counter is incremented at each Burst Clock K rising edge. The Synchronous Burst Read timing diagrams and AC Characteristics are described in the AC and DC Parameters section. See Figures 13, 14, 15 and 16, and Table 20. Synchronous Burst Read Suspend. During a Synchronous Burst Read operation it is possible to suspend the operation, freeing the data bus for other higher priority devices. A valid Synchronous Burst Read operation is suspended when both Output Enable and Burst Address Advance are High, VIH. The Burst Address Advance going High, VIH, stops the burst counter and the Output Enable going High, VIH, inhibits the data outputs. The Synchronous Burst Read operation can be resumed by setting Output Enable Low.
E VIL VIL VIL VIL VIL VIH X
G VIH VIL VIH VIL VIH X X
GD X VIH X VIH X X X
RP VIH VIH VIH VIH VIH VIH VIL
K R(3) R(3) X R(3) R(3) X X
L VIL VIH VIH VIH VIH X X
B X VIL VIH VIL VIL X X
A0-A19 DQ0-DQ31 Address Input Data Output High Z Data Output High Z High Z High Z
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Burst Configuration Register The Burst Configuration Register is used to configure the type of bus access that the memory will perform. The Burst Configuration Register is set through the Command Interface and will retain its information until it is re-configured, the device is reset, or the device goes into Reset/Power-Down mode. The Burst Configuration Register bits are described in Table 6. They specify the selection of the burst length, burst type, burst X and Y latencies and the Read operation. Refer to Figure 5 for examples of synchronous burst configurations. Read Select Bit (M15). The Read Select bit, M15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to '1', Bus Read operations are asynchronous; when the Read Select but is set to '0', Bus Read operations are synchronous. On reset or power-up the Read Select bit is set to'1' for asynchronous accesses. Standby Disable Bit (M14). The Standby Disable Bit, M14, is used to disable the Standby mode. When the Standby bit is `1', the device will not enter Standby mode when Chip Enable goes High, VIH. X-Latency Bits (M13-M11). The X-Latency bits are used during Synchronous Bus Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 6., Burst Configuration Register. The X-Latency bits should also be selected in accordance with Note: 1. below Table 6., Burst Configuration Register. Y-Latency Bit (M9). The Y-Latency bit is used during Synchronous Bus Read operations to set the number of clock cycles between consecutive reads. The Y-Latency value depends on both the X-Latency value and the setting in M9. When the Y-Latency is 1 the data changes each clock cycle; when the Y-Latency is 2 the data changes every second clock cycle. See Table 6., Burst Configuration Register and Note 2.for valid combinations of the Y-Latency, the X-Latency and the Clock frequency. Valid Data Ready Bit (M8). The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When the Valid Data Ready bit is '0' the Valid Data Ready output pin is driven Low for the rising clock edge when invalid data is output on the bus. When the Valid Data Ready bit is '1' the Valid Data Ready output pin is driven Low one clock cycle prior to invalid data being output on the bus. Wrap Burst Bit (M3). The burst reads can be confined inside the 4 or 8 Word boundary (wrap) or overcome the boundary (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When the Wrap Burst bit is set to `0' the burst read wraps; when it is set to `1' the burst read does not wrap. Burst Length Bit (M2-M0). The Burst Length bits set the maximum number of Double-Words that can be output during a Synchronous Burst Read operation before the address wraps. Burst lengths of 4 or 8 and continuous burst are available. Table 6., Burst Configuration Register gives the valid combinations of the Burst Length bits that the memory accepts; Table 7., Burst Type Definition, gives the sequence of addresses output from a given starting address for each length. If either a Continuous or a No Wrap Burst Read has been initiated the device will output data synchronously. Depending on the starting address, the device activates the Valid Data Ready output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 Double Word boundary, the continuous burst mode will run without activating the Valid Data Ready output. If the starting address is not aligned to a 4 Double Word boundary, Valid Data Ready is activated to indicate that the device needs an internal delay to read the successive words in the array. M10, M7 to M4 are reserved for future use.
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Table 6. Burst Configuration Register
Bit M15 Description 0 Read Select 1 0 M14 Standby Disable 1 001 010 M13-M11 X-Latency (1) 011 100 101 110 M10 M9 Reserved Y-Latency (2) 0 1 0 M8 M7-M4 M3 Valid Data Ready 1 Reserved 0 Wrapping 1 001 M2-M0 Burst Length 010 111 No Wrap 4 Double-Words 8 Double-Words Continuous Wrap R valid Low one data cycle before valid Burst Clock edge One Burst Clock cycle Two Burst Clock cycles R valid Low during valid Burst Clock edge Standby Mode Disabled 3 4 5 6 7 8 Asynchronous Read (Default at power-up) Standby Mode Enabled (Default at power-up) Value Synchronous Burst Read Description
Note: 1. X latencies can be calculated as: (tAVQV - tLLKH + tKHQV) + tSYSTEM MARGIN < (X -1) tK. (X is an integer number from 4 to 8 and tK is the clock period), , where tLLKH is the value given by the master microcontroller timing specifications. 2. Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tKHQV < Y tK. 3. tSYSTEM MARGIN is the time margin required for the calculation.
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Table 7. Burst Type Definition
M3 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Starting Address 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 x4 Sequential 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 - - - - - 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 4-5-6-7 5-6-7-8 6-7-8-9 7-8-9-10 8-9-10-11 x8 Sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 - 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 8-9-10-11-12-13-14-15 Continuous 0-1-2-3-4-5-6-7-8-9-10.. 1-2-3-4-5-6-7-8-9-10-11.. 2-3-4-5-6-7-8-9-10-11-12.. 3-4-5-6-7-8-9-10-11-12-13.. 4-5-6-7-8-9-10-11-2-13-14.. 5-6-7-8-9-10-11-12-13-14.. 6-7-8-9-10-11-12-13-14-15.. 7-8-9-10-11-12-13-14-15-16.. 8-9-10-11-12-13-14-15-16-17.. 0-1-2-3-4-5-6-7-8-9-10.. 1-2-3-4-5-6-7-8-9-10-11.. 2-3-4-5-6-7-8-9-10-11-12.. 3-4-5-6-7-8-9-10-11-12-13.. 4-5-6-7-8-9-10-11-12-13-14.. 5-6-7-8-9-10-11-12-13-14.. 6-7-8-9-10-11-12-13-14-15.. 7-8-9-10-11-12-13-14-15-16.. 8-9-10-11-12-13-14-15-16-17..
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Figure 5. Example Burst Configuration X-1-1-1
0 K 1 2 3 4 5 6 7 8 9
ADD
VALID
L
DQ
3-1-1-1
VALID
VALID
VALID
VALID
VALID
VALID
VALID
DQ
4-1-1-1
VALID
VALID
VALID
VALID
VALID
VALID
DQ
5-1-1-1
VALID
VALID
VALID
VALID
VALID
DQ DQ DQ
6-1-1-1
VALID
VALID VALID
VALID
VALID VALID VALID
7-1-1-1
VALID VALID
8-1-1-1
AI03841b
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COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. The Commands are summarized in Table 8., Commands. Refer to Table 8 in conjunction with the text descriptions below. Read Memory Array Command The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will output the addressed memory array data. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read commands will access the memory array. Read Electronic Signature Command The Read Electronic Signature command is used to read the Manufacturer Code, the Device Code, the Block Protection Configuration Register and the Burst Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued, subsequent Bus Read operations, depending on the address specified, read the Manufacturer Code, the Device Code, the Block Protection Configuration or the Burst Configuration Register until another command is issued; see Table 9., Read Electronic Signature. Read Query Command The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations, depending on the address specified, read from the Common Flash Interface Memory Area. Read Status Register Command The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. The Status Register information is present on the output data bus (DQ0-DQ7) when Chip Enable E and Output Enable G are at VIL and Output Disable is at VIH. An interactive update of the Status Register bits is possible by toggling Output Enable or Output Disable. It is also possible during a Program or Erase operation, by disactivating the device with Chip Enable at VIH and then reactivating it with Chip Enable and Output Enable at VIL and Output Disable at VIH. The content of the Status Register may also be read at the completion of a Program, Erase or Suspend operation. During a Block Erase, Program, Tuning Protection Program or Tuning Protection Unlock command, DQ7 indicates the Program/Erase Controller status. It is valid until the operation is completed or suspended. See the section on the Status Register and Table 11 for details on the definitions of the Status Register bits. Clear Status Register Command The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to `0'. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent Bus Read operations continue to output the same data. The bits in the Status Register are sticky and do not automatically return to `0' when a new Program, Erase, Block Protect or Block Unprotect command is issued. If any error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command. Block Erase Command The Block Erase command can be used to erase a block. It sets all of the bits in the block to `1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write operations are required to issue the command; the first write cycle sets up the Block Erase command, the second write cycle confirms the Block erase command and latches the block address in the internal state machine and starts the Program/Erase Controller. The sequence is aborted if the Confirm command is not given and the device will output the Status Register Data with bits 4 and 5 set to '1'. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Erase operation the memory will only accept the Read Status Register command and the Program/ Erase Suspend command. All other commands will be ignored. The command can be executed using VDD. If VPEN is at VIH, the operation can be performed. If VPEN goes below VIH, the operation aborts, the VPEN Status bit in the Status Register is set to `1' and the command must be re-issued.
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Typical Erase times are given in Table 10. See Appendix A, Figure 22., Block Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Block Erase command. Erase All Main Blocks Command The Erase All Main Blocks command is used to erase all 63 Main Blocks, without affecting the Parameter Blocks. Issuing the Erase All Main Blocks command sets every bit in each Main Block to '1'. All data previously stored in the Main Blocks are lost. Two Bus Write cycles are required to issue the Erase All Main Blocks command. The first cycle sets up the command, the second cycle confirms the command and starts the Program/Erase Controller. If the Confirm Command is not given the sequence is aborted, and Status Register bits 4 and 5 are set to '1'. If the address given in the second cycle is located in a protected block, the Erase All Main Blocks operation aborts. The data remains unchanged in all blocks and the Status Register outputs the error. Once the Erase All Main Blocks command has been issued, subsequent Bus Read operations output the Status Register. See the STATUS REGISTER section for details. During an Erase All Main Blocks operation, only the Read Status Register command is accepted by the memory; any other command are ignored. Erase All Main Blocks, once started, cannot be suspended. The Erase All Main Blocks command can be executed using VDD. If VPEN is at VIH, the operation will be performed. If VPEN is lower than VIH the operation aborts and the Status Register VPEN bit (bit 3) is set to '1'. Program Command The Program command is used to program the memory array. Two Bus Write operations are required to issue the command; the first write cycle sets up the Program command, the second write cycle latches the address and data to be programmed and starts the Program/Erase Controller. A program operation can be aborted by writing FFFFFFFFh to any address after the program setup command has been given. The Program command is also used to program the OTP block. Refer to Table 8., Commands, for details of the address. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. If Reset/Power-down, RP, falls to VIL during programming the operation will be aborted. The command can be executed using VDD. If VPEN is at VIH, the operation can be performed. If VPEN goes below VIH, the operation aborts, the VPEN Status bit in the Status Register is set to `1' and the command must be re-issued. See Appendix A, Figure 20., Program Flowchart and Pseudo Code, for a suggested flowchart on using the Program command. Write to Buffer and Program Command The Write to Buffer and Program Command makes use of the device's double Word (32 bit) Write Buffer to speed up programming. Up to eight Double Words can be loaded into the Write Buffer and programmed into the memory. Four successive steps are required to issue thecommand. 1. One Bus Write operation is required to set up the Write to Buffer and Program Command. Any Bus Read operations will start to output the Status Register after the 1st cycle. 2. Use one Bus Write operation to write the selected memory Block Address (any address in the block where the values will be programmed can be used) along with the value N on the Data Inputs/Outputs, where N+1 is the number of Words to be programmed. The maximum value of N+1 is 8 Words. 3. Use N+1 Bus Write operations to load the address and data for each Word into the Write Buffer. The address must be between Start Address and Start Address plus N, where Start Address is the first word address. 4. Finally, use one Bus Write operation to issue the final cycle to confirm the command and start the Program operation. If any address is outside the block boundaries or if the correct sequence is not followed, Status Register bits 4 and 5 are set to `1' and the operation will abort without affecting the data in the memory array. A protected block must be unprotected using the Blocks Unprotect command. During a Write to Buffer and Program operation the memory will only accept the Read Status Register and the Program/Erase Suspend commands. All other commands are ignored. The Write to Buffer and Program command can be executed using VDD. If VPEN is at VIH, the operation will be performed. If VPEN is lower than VIH the operation aborts and the Status Register VPEN bit (bit 3) is set to '1'.
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The Status Register should be cleared before reissuing the command. Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Erase operation. The command will only be accepted during a Program or Erase operation. It can be issued at any time during a program or erase operation. The command is ignored if the device is already in suspend mode. One Bus Write cycle is required to issue the Program/Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase Controller has paused; no other commands will be accepted until the Program/ Erase Controller has paused. After the Program/ Erase Controller has paused, the memory will continue to output the Status Register until another command is issued. During the polling period between issuing the Program/Erase Suspend command and the Program/ Erase Controller pausing it is possible for the operation to complete. Once the Program/Erase Controller Status bit (bit 7) indicates that the Program/Erase Controller is no longer active, the Program Suspend Status bit (bit 2) or the Erase Suspend Status bit (bit 6) can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 10. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature, Read Query and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Erase then the Program, the Write to Buffer and Program, the Set/Clear Block Protection Configuration Register and the Program Suspend commands will also be accepted. When a program operation is completed inside a Block Erase Suspend the Read Memory Array command must be issued to reset the device in Read mode, then the Erase Resume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly. See Appendix A, Figure 21., Program Suspend & Resume Flowchart and Pseudo Code, and Figure 23., Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. See Appendix A, Figure 21., Program Suspend & Resume Flowchart and Pseudo Code, and Figure 23., Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command. Set Burst Configuration Register Command. The Set Burst Configuration Register command is used to write a new value to the Burst Configuration Register which defines the burst length, type, X and Y latencies, Synchronous/Asynchronous Read mode. Two Bus Write cycles are required to issue the Set Burst Configuration Register command. The first cycle writes the setup command. The second cycle writes the address where the new Burst Configuration Register content is to be written, and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to `1'. Once the command is issued the memory returns to Read mode as if a Read Memory Array command had been issued. The value for the Burst Configuration Register is always presented on A0-A15. M0 is on A0, M1 on A1, etc.; the other address bits are ignored. Tuning Protection Unlock Command The Tuning Protection Unlock command unlocks the tuning protected blocks by writing the 64bit Tuning Protection Code (M58BW032B only). After a reset or power-up the blocks are locked and so a Tuning Protection Unlock command must be issued to allow program or erase operations on tuning protected block or to program a new Tuning Protection Code. Read operations output the Status Register content after the unlock operation has started. The Tuning Protection Code is composed of 64 bits, but the data bus is 32 bits wide so four (2 x 2) write cycles are required to unlock the device. The first write cycle issues the Tuning Protection Unlock Setup command (78h). The second write cycle inputs the first 32 bits of the tuning protection code on the data bus, at address 00000h. Bit 7 of the Status Register should now be checked to verify that the device has successfully stored the first part of the code in the internal register. If b7 = `1', the device is ready to accept the second part of the code. This does not mean that the first 32 bits match the tuning protection code, simply that it was correctly stored for the comparing. If b7 = `0', the user must wait for this bit setting (refer to write cycle AC timings).
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The third write cycle re-issues the Tuning Protection Unlock Setup command (78h). The fourth write cycle inputs the second 32 bits of the code at address 00001h. Bit 7 of the Status Register should again be checked to verify that the device has successfully stored the second part of the code. When the device is ready (b7 = `1'), the tuning protection status can be monitored on Status Register bit0. If b0 = `0' the device is locked; b0 = `1' the device is unlocked. If the device is still locked a Read Memory Array command must be issued before re-issuing the Tuning Protection Unlock command. Device locked means that the 64 bit password is wrong. If the unlock operation is attempted using a wrong code on an already unlocked device, the device becomes locked. Status register bit 4 is set to '1' if there has been a verify failure. Tuning Protection Unlock command aborts if VPEN drops below VIH or RP goes to VIL. Once the device is successfully unlocked, a Read Memory Array command must be issued to return the memory to read mode before issuing any other commands. The user can then program or erase all blocks, depending on WP and VPEN status and on the protection status of each block. At this point, it is also possible to configure a new protection code. To write a new protection code into the device tuning register, the user must perform the Tuning Protection Program sequence. The device can be re-locked with a reset or power-down. See Appendix A, Figure 24, 25 and 26 for suggested flowcharts for using the Tuning Protection Unlock command. Tuning Protection Program Command. The Tuning Protection Program command is used to program a new Tuning Protection Code which can be configured by the designer of the application (M58BW032B only). The device should be unlocked by the Tuning Protection Unlock command before issuing the Tuning Protection Program command. Read operations output the Status Register content after the program operation has started. The Tuning Protection Code is composed of 64 bits, but the data bus is 32 bits wide so four (2 x 2) write cycles are required to program the code. The first write cycle issues the Tuning Protection Program Setup command (48h). The second write cycle inputs the first 32 bits of the new tuning protection code on the data bus, at address 00000h. Bit 7 of the Status Register should now be checked to verify that the device has successfully stored the first part of the code in the internal register. If b7 = `1', the device is ready to accept the
second part of the code. If b7 = `0', the user must wait for this bit setting (refer to write cycle AC timings). The third write cycle re-issues the Tuning Protection Program Setup command (48h). The fourth write cycle inputs the second 32 bits of the new code at address 00001h. Bit 7 of the Status Register should again be checked to verify that the device has successfully stored the second part of the code. When the device is ready (b7 = `1'). After completion Status Register bit 4 is set to '1' if there has been a program failure. Programming aborts if VPEN drops below VIH or RP goes to VIL. A Read Memory Array command must be issued to return the memory to read mode before issuing any other commands. Once the code has been changed a device reset or power-down will make the protection active with the new code. See Appendix A, Figure 24, 25 and 26 for suggested flowcharts for using the Tuning Protection Program command. Set Block Protection Configuration Register Command The Set Block Protection Configuration Register command is used to configure the Block Protection Configuration Register to `Protected', for a specific block. Protected blocks are fully protected from program or erase when WP pin is Low, VIL. The status of a protected block can be changed to `Unprotected' by using the Clear Block Protection Configuration Register command. At power-up, all block are configured as `Protected'. Two bus operations are required to issue a Set Block Protection Configuration Register command: The first cycle writes the setup command The second write cycle specifies the address of the block to protect and confirms the command. If the command is not confirmed, the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to `1'. To protect multiple blocks, the Set Block Protection Configuration Register command must be repeated for each block. Any attempt to re-protect a block already protected does not change its status. Clear Block Protection Configuration Register Command. The Clear Block Protection Configuration Register command is used to configure the Block Protection Configuration Register to `Unprotected', for a
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specific block thus allowing program/erase operations to this block, regardless of the WP pin status. Two bus operations are required to issue a Clear Block Protection Configuration Register command: The first cycle writes the setup command The second write cycle specifies the address of the block to unprotect and confirms the command. If the command is not confirmed, Table 8. Commands
Cycles Bus Operations 1st Cycle Op. Addr. Data X X X X X 55h 55h AAh AAh AAh X X X AAh X X X Op. 2nd Cycle Addr. Data RA RD 3rd Cycle 4th Cycle Command
the sequence is aborted and the device outputs the Status Register with bits 4 and 5 set to `1'. To unprotect multiple blocks, the Clear Block Protection Configuration Register command must be repeated for each block. Any attempt to unprotect a block already unprotected does not affect its status.
Op. Addr. Data Op. Addr. Data
Read Memory Array Read Electronic Signature(2) Read Status Register Read Query Clear Status Register Block Erase Erase All Main Blocks any block Program OTP Block Write to Buffer and Program Program/Erase Suspend Program/Erase Resume Set Burst Configuration Register Tuning Protection Program(3) Tuning Protection Unlock(3) Set Block Protection Configuration Register Clear Block Protection Configuration Register
2 Write 2 Write 1 Write
FFh Read
90h Read IDA(1) IDD(1) 70h 98h Read 50h 20h Write 80h Write 40h Write 10h 40h Write E8h Write B0h D0h 60h Write BCRh 03h Read RA RD BA AAh PA PA BA D0h D0h PD PD N Write PA PD Write X D0h RA RD
2 Write 1 2 2 2 2 Write Write Write Write Write
N+4 Write 1 1 3 4 4 2 2 Write Write Write Write Write Write Write
48h Write TPAh TPCh Write AAh 48h Write TPAh TPCh 78h Write TPAh TPCh Write 60h Write 60h Write BA BA 01h D0h X 78h Write TPAh TPCh
Note: 1. X Don't Care; RA Read Address, RD Read Data, ID Device Code, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, BCR Burst Configuration Register value, TPA = Tuning Protection Address, TPC = Tuning Protection Code, N+1 number of Words to program, BA Block address. 2. The Manufacturer Code, the Device Code, the Burst Configuration Register, and the Block Protection Configuration Register of each block are read using the Read Electronic Signature command. 3. Cycles 1 and 2 input the first 32 bits of the code, cycles 3 and 4 the second 32 bits of the code.
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Table 9. Read Electronic Signature
Code Manufacturer Device M58BW032xB(1) Burst Configuration Register Block Protection Configuration Register All 00001h 00005h SBA+02h(3) 00008837h BCR(2) 00000000h (Unprotected) 00000001h (Protected) Device All M58BW032xT(1) A19-A0 00000h 00001h DQ31-DQ0 00000020h 00008838h
Note: 1. x= B or D version of the device. 2. BCR= Burst Configuration Register. 3. SBA is the start address of each block.
Table 10. Program, Erase Times and Program Erase Endurance Cycles
M58BW032B/D Parameters Min Full Chip Program Double Word Program 512 Kbit Block Erase 256 Kbit Block Erase 64 Kbit Block Erase Program Suspend Latency Time Erase Suspend Latency Time Program/Erase Cycles (per Block)
Note: TA = -40 to 125C, VDD = 3.0V to 3.6V, VDDQ = 1.6V to VDD
Unit Typ 15 TBD 1 0.8 0.6 3 10 Max 20 TBD 2 1.6 1.2 10 30 100,000 s s s s s s s cycles
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
STATUS REGISTER
The Status Register provides information on the current or previous Program, Erase, Block Protect or Tuning Protection operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Program/Erase Resume commands. The Status Register can be read from any address. The contents of the Status Register can be updated during an erase or program operation by toggling the Output Enable or Output Disable pins or by dis-activating (Chip Enable, VIH) and then reactivating (Chip Enable and Output Enable, VIL, and Output Disable, VIH.) the device. The Status Register bits are summarized in Table 11., Status Register Bits. Refer to Table 11 in conjunction with the following text descriptions. Program/Erase Controller Status (Bit 7) The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is set to `0', the Program/Erase Controller is active; when bit7 is set to `1', the Program/Erase Controller is inactive. The Program/Erase Controller Status is set to `0' immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is set to `1'. During Program and Erase operations the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is set to `1'. After the Program/Erase Controller completes its operation the Erase Status (bit5), Program/Tuning Protection Unlock status (bit4) bits should be tested for errors. Erase Suspend Status (Bit 6) The Erase Suspend Status bit indicates that an Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is set to `1' (Program/Erase Controller inactive); after a Program/ Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is set to `0', the Program/Erase Controller is active or has completed its operation; when the bit is set to `1', a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to `0'. Erase Status (Bit 5) The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Erase Status bit is set to `0', the memory has successfully verified that the block has erased correctly. When the Erase Status bit is set to `1', the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. Once set to `1', the Erase Status bit can only be reset to `0' by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program/ Write to Buffer and Program/Tuning Protection Unlock Status (Bit 4) The Program/Write to Buffer and Program/Tuning Protection Unlock Status bit is used to identify a Program failure, a Write to Buffer and Program failure or a Tuning Protection Code verify failure. Bit4 should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When bit4 is set to `0' the memory has successfully verified that the device has programmed correctly or that the correct Tuning Protection Code has been written. When bit4 is set to `1' the device has failed to verify that the data has been programmed correctly or that the correct Tuning Protection code has been written. Once set to 1', the Program Status bit can only be reset to `0' by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. VPEN Status (Bit 3). The VPEN Status bit can be used to identify if a program or erase operation has been attempted when VPEN is Low, VIL. When Bit 3 is set to `0' no program or erase operations have been attempted with VPEN Low, VIL, since the last Clear Status Register command, or hardware reset. When Bit 3 is set to `1' a program or erase operation has been attempted with VPEN Low, VIL. Once set to `1', Bit 3 can only be reset by an Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new program
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
or erase command is issued, otherwise the new command will appear to fail. Program Suspend Status (Bit 2) The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is set to `1' (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is set to `0', the Program/Erase Controller is active or has completed its operation; when the bit is set to `1', a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns to `0'. Block Protection Status (Bit 1) The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a protected block. Table 11. Status Register Bits
Bit 7 Program/Erase Controller Status '0' 6 Erase Suspend Status '0' 5 Erase Status '0' 4 Program Status, Tuning Protection Unlock Status VPEN Status bit 2 Program Suspend Status '0' 1 Erase/Program in a Protected Block 0 Tuning Protection Status '0'
Note: 1. For the M58BW032D version the Tuning Protection Status bit is always set to `1'.
When the Block Protection Status bit is set to `0', no Program or Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is set to `1', a Program or Erase operation has been attempted on a protected block. Once set to `1', the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set to `1' it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Tuning Protection Status (Bit 0) The Tuning Protection Status bit indicates if the device is locked (Tuning Protection is enabled) or unlocked (Tuning Protection is disabled). When the Tuning Protection Status bit is set to `0' the device is locked, when it is set to `1' the device is unlocked. After a reset or power-up the device is locked and so bit0 is set to `0'. The Tuning Protection Status bit is set to `1' for the M58BW032D version.
Name
Logic Level '1' Ready Busy Suspended
Definition
'1'
In Progress or Completed Erase Error Erase Success Program Error Program Success no program or erase attempted program or erase attempted Suspended In Progress or Completed program/erase on protected block, abort No operations to protected blocks Tuning Protection Disabled(1) Tuning Protection Enabled
'1'
'1' '0' `0' `1' '1'
3
'1' '0' '1'
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MAXIMUM RATING
Stressing the device above the ratings listed in Table 12., Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 12. Absolute Maximum Ratings
Value Symbol TBIAS TSTG TLEAD VIO VDD, VDDQ, VDDQIN Parameter Min Temperature Under Bias Storage Temperature Lead Temperature during Soldering(1) Input or Output Voltage Supply Voltage -0.6 -0.6 -40 -55 Max 125 155 TBD VDDQ +0.6 VDDQIN +0.6 4.2 C C C V V Unit
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Compliant with the ECOPACK(R) 7191395 specification for Lead-free soldering processes.
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 13., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 13. Operating and AC Measurement Conditions
Value Parameter Min Supply Voltage (VDD) Input/Output Supply Voltage (VDDQ) Grade 6 Ambient Temperature (TA) Load Capacitance (CL) Clock Rise and Fall Times Input Rise and Fall Times Input Pulses Voltages Input and Output Timing Ref. Voltages 0 to VDDQ VDDQ/2 Grade 3 3.0 2.4 -40 -40 30 3 3 Max 3.6 3.6 90 125 V V C C pF ns ns V V Units
Figure 6. AC Measurement Input Output Waveform
VDDQ VDDQIN
Figure 7. AC Measurement Load Circuit
VDDQ/2 VDDQIN/2
DEVICE UNDER TEST CL
OUT
0V
AI04153
CL includes JIG capacitance
Note: VDD = VDDQ.
AI04154b
Table 14. Device Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Typ 6 8 Max 8 12 Unit pF pF
Note: 1. TA = 25C, f = 1 MHz 2. Sampled only, not 100% tested.
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Table 15. DC Characteristics
Symbol ILI ILO IDD(1) IDDB(1) IDD1(1) IDD2(1) IDD3(1) VIL VIH VIH VOL VOH VLKO Parameter Input Leakage Current Output Leakage Current Supply Current (Random Read) Supply Current (Burst Read) Supply Current (Standby) Supply Current (Program or Erase) Supply Current (Erase/Program Suspend) Input Low Voltage Input High Voltage (for DQ lines) Input High Voltage (for Input only lines) Output Low Voltage Output High Voltage CMOS VDD Supply Voltage (Erase and Program lockout) IOL = 100A IOH = -100A VDDQ -0.1 2.2 Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH, fadd = 6MHz E = VIL, G = VIH, fclock = 75MHz E = RP = VDD 0.2V Program, Erase in progress E = VIH -0.5 0.8VDDQIN 0.8VDDQIN Min Max 1 5 50 50 100 30 40 0.2VDDQIN VDDQ +0.3 3.6 0.1 Unit A A mA mA A mA A V V V V V V
Note: 1. The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst Configuration Register to `1'.
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 8. Asynchronous Bus Read AC Waveforms
tAVAV A0-A19 tAVQV tLLEL L tELQX tELQV E tGLQX tGLQV G tAXQX tEHLX VALID
tEHQX tEHQZ
GD tGHQX tGHQZ DQ0-DQ31 OUTPUT
See also Page Read
AI08921
Table 16. Asynchronous Bus Read AC Characteristics.
M58BW032 Symbol tAVAV tAVQV tAXQX tEHLX tEHQX tEHQZ tELQV(1) tELQX tGHQX tGHQZ tGLQV tGLQX tLLEL Parameter Address Valid to Address Valid Address Valid to Output Valid Address Transition to Output Transition Chip Enable High to Latch Enable Transition Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable to Output Transition Latch Enable Low to Chip Enable Low G = VIL G = VIL G = VIL G = VIL E = VIL E = VIL E = VIL E = VIL Test Condition 45 E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL Min Max Min Min Min Max Max Min Min Max Max Min Min 45 45 0 0 0 20 45 0 0 15 15 0 0 55 60 55 55 55 60 60 60 ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Output Enable G may be delayed up to tELQV - tGLQV after the falling edge of Chip Enable E without increasing tELQV.
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 9. Asynchronous Latch Controlled Bus Read AC Waveforms
A0-A19 tAVLL
VALID tLHAX
L
tLHLL
tLLLH tELLL
tEHLX
E tGLQX tGLQV G tLLQX tLLQV DQ0-DQ31 OUTPUT See also Page Read
AI08922
tEHQX tEHQZ
tGHQX GHQZ
Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics
M58BW032 Symbol tAVLL tEHLX tEHQX tEHQZ tELLL tGHQX tGHQZ tGLQV tGLQX tLHAX tLHLL tLLLH tLLQV tLLQX Parameter Address Valid to Latch Enable Low Chip Enable High to Latch Enable Transition Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Latch Enable Low Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Latch Enable High to Address Transition Latch Enable High to Latch Enable Low Latch Enable Low to Latch Enable High Latch Enable Low to Output Valid Latch Enable Low to Output Transition E = VIL E = VIL, G = VIL E = VIL, G = VIL E = VIL E = VIL E = VIL E = VIL E = VIL G = VIL G = VIL Test Condition 45 E = VIL Min Min Min Max Min Min Max Max Min Min Min Min Max Min 0 0 0 20 0 0 15 15 0 5 10 10 45 0 55 0 0 0 20 0 0 15 25 0 5 10 10 55 0 60 0 0 0 20 0 0 15 25 0 5 10 10 60 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 10. Asynchronous Page Read AC Waveforms
A0-A1
A0 and/or A1 tAVQV1 tAXQX
DQ0-DQ31
OUTPUT
OUTPUT + 1
AI03646
Table 18. Asynchronous Page Read AC Characteristics
M58BW032 Symbol tAVQV1 tAXQX Parameter Address Valid to Output Valid Address Transition to Output Transition Test Condition 45 E = VIL, G = VIL E = VIL, G = VIL Max Min 25 6 55 25 6 60 25 6 ns ns Unit
Note: For other timings see Table 16., Asynchronous Bus Read AC Characteristics..
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VALID tWHAX VALID VALID tWHEH tELWL tWLWH tWHGL tWHWL tDVWH INPUT tWHDX INPUT tWHQV VALID SR tVPHWH tQVVPL tPHWH RP = VHH tQVPL RP = VDD Write Cycle Write Cycle Read Status Register
AI08923b
A0-A19
tAVWH
E=L
tAVLL
G
Figure 11. Asynchronous Write AC Waveform
W
DQ0-DQ31
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
VPEN
RP
A0-A19 VALID tLHAX VALID VALID
tAVLH
L tWHAX tLLWH tELLL
tLLLH
tAVLL
E tAVWH
G tWHEH tWHWL tWHGL
tELWL tWLWH
W tDVWH INPUT tWHDX tVPHWH INPUT tWHQV VALID SR tQVVPL
Figure 12. Asynchronous Latch Controlled Write AC Waveform
DQ0-DQ31
VPEN tQVPL RP = VHH RP = VDD
RP
Write Cycle
Write Cycle
Read Status Register
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
AI08924b
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Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics
M58BW032 Symbol tAVLL tAVWH tDVWH tELLL tELWL tLHAX tLLLH tLLWH tQVVPL tVPHWH tWHAX tWHDX tWHEH tWHGL tWHQV tWHWL tWLWH tQVPL Parameter Address Valid to Latch Enable Low Address Valid to Write Enable High Data Input Valid to Write Enable High Chip Enable Low to Latch Enable Low Chip Enable Low to Write Enable Low Latch Enable High to Address Transition Latch Enable Low to Latch Enable High latch Enable Low to Write Enable High Output Valid to VPEN Low VPEN High to Write Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Output Enable Low Write Enable High to Output Valid Write Enable High to Write Enable Low Write Enable Low to Write Enable High Output Valid to Reset/Power-down Low E = VIL E = VIL E = VIL E = VIL E = VIL E = VIL Test Condition 45 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 0 25 25 0 0 5 10 25 0 0 0 0 0 150 175 20 25 0 55 0 25 25 0 0 5 10 25 0 0 0 0 0 150 175 20 25 0 60 0 25 25 0 0 5 10 25 0 0 0 0 0 150 175 20 25 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
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0 1
n
n+1
n+2
K tKHAX VALID tLLKH tKHLX
tKHLL
A0-A19
L tAVLL tELLL tAVQV tEHQX tEHQZ
E tGLQV tGHQX tGHQZ
G
tKHQV OUTPUT
Figure 13. Synchronous Burst Read (Data Valid from 'n' Clock Rising Edge)
DQ0-DQ31
Setup
Note: n depends on Burst X-Latency. AI08925b
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Table 20. Synchronous Burst Read AC Characteristics
M58BW032 Symbol tAVLL tBHKH tBLKH tELLL tGLQV tKHAX tKHLL tKHLX tKHQX tLLKH tRLKH tKHQV Parameter Address Valid to Latch Enable Low Burst Address Advance High to Valid Clock Edge Burst Address Advance Low to Valid Clock Edge Chip Enable Low to Latch Enable low Output Enable Low to Output Valid Valid Clock Edge to Address Transition Valid Clock Edge to Latch Enable Low Valid Clock Edge to Latch Enable Transition Valid Clock Edge to Output Transition Latch Enable Low to Valid Clock Edge Valid Data Ready Low to Valid Clock Edge Valid Clock Edge to Output Valid E = VIL, L = VIH E = VIL E = VIL E = VIL E = VIL, G = VIL, L = VIH E = VIL E = VIL, G = VIL, L = VIH E = VIL, G = VIL, L = VIH Test Condition 45 E = VIL E = VIL, G = VIL, L = VIH E = VIL, G = VIL, L = VIH Min Min Min Min Min Min Min Min Min Min Min Max 0 8 8 0 10 5 0 0 0 6 6 8 55 0 8 8 0 10 5 0 0 0 6 6 8 60 0 8 8 0 10 5 0 0 0 6 6 8 ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Data output should be read on the valid clock edge. 2. For other timings see Table 16., Asynchronous Bus Read AC Characteristics..
Figure 14. Synchronous Burst Read (Data Valid from 'n' Clock Rising Edge)
n K tKHQV
n+1
n+2
n+3
n+4
n+5
DQ0-DQ31
Q0
Q1 tKHQX
Q2
Q3
Q4
Q5
SETUP
Burst Read Q0 to Q3
Note: n depends on Burst X-Latency AI04408c
Note: For set up signals and timings see Synchronous Burst Read.
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Figure 15. Synchronous Burst Read - Continuous - Valid Data Ready Output
K
Output (1)
V
V
V tRLKH
V
V
R
(2)
AI03649b
Note: Valid Data Ready = Valid Low during valid clock edge 1. V= Valid output. 2. The internal timing of R follows DQ.
Figure 16. Synchronous Burst Read - Burst Address Advance
K
A0-A19
VALID
L
DQ0-DQ31 tGLQV G tBLKH B
Q0
Q1
Q2
tBHKH
AI03650
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Figure 17. Reset, Power-Down and Power-up AC Waveform
W, E, G
tPHWL tPHEL tPHGL
tPLRH
R tPHWL tPHEL tPHGL RP tVDHPH VDD, VDDQ Power-Up Reset
AI03849b
tPLPH
Table 21. Reset, Power-Down and Power-up AC Characteristics
Symbol tPHEL tPHQV (1) tPHWL tPHGL tPLPH tPLRH tVDHPH Parameter Reset/Power-down High to Chip Enable Low Reset/Power-down High to Output Valid Reset/Power-down High to Write Enable Low Reset/Power-down High to Output Enable Low Reset/Power-down Low to Reset/Power-down High Reset/Power-down Low to Valid Data Ready High Supply Voltages High to Reset/Power-down High 50 50 100 2 10 30 Min 50 130 Max Unit ns ns ns ns ns s s
Note: 1. This time is tPHEL + tAVQV or tPHEL + tELQV.
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
PACKAGE MECHANICAL
Figure 18. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline
D FD FE SD D1
SE E E1 BALL "A1" ddd
e e A A1 b A2
BGA-Z05
Note: Drawing is not to scale.
Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 12.000 9.000 1.000 1.500 1.500 0.500 0.500 - - - - - - - 0.400 1.100 0.500 10.000 7.000 - - - - - - 0.150 - - - - - - - 0.4724 0.3543 0.0394 0.0591 0.0591 0.0197 0.0197 - - - - - - - 0.350 Min Max 1.700 0.450 0.0157 0.0433 0.0197 0.3937 0.2756 - - - - - - 0.0059 - - - - - - - 0.0138 Typ Min Max 0.0669 0.0177 inches
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 19. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline
Ne A2
N 1
e Nd D2 D1 D b
E2 E1 E L1
A CP
c
QFP-B
A1
L
Note: Drawing is not to scale.
Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data
Symbol A A1 A2 b c D D1 D2 e E E1 E2 L L1 N Nd Ne 23.200 20.000 18.400 0.800 17.200 14.000 12.000 0.800 1.600 2.800 0.250 2.550 0.300 0.130 22.950 19.900 - - 16.950 13.900 - 0.650 - 0 80 24 16 3.050 0.450 0.230 23.450 20.100 - - 17.450 14.100 - 0.950 - 7 0.9134 0.7874 0.7244 0.0315 0.6772 0.5512 0.4724 0.0315 0.0630 0.1102 millimeters Typ Min Max 3.400 0.0098 0.1004 0.0118 0.0051 0.9035 0.7835 - - 0.6673 0.5472 - 0.0256 - 0 80 24 16 0.1201 0.0177 0.0091 0.9232 0.7913 - - 0.6870 0.5551 - 0.0374 - 7 Typ inches Min Max 0.1339
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
PART NUMBERING
Table 24. Ordering Information Scheme
Example: Device Type M58 Architecture B = Burst Mode Operating Voltage W = VDD = 3.0V to 3.6V; VDDQ = VDDQIN =1.6 to VDD Device Function 032B = 32 Mbit (x32), Boot Block, Burst Tuning Protection 032D = 32 Mbit (x32), Boot Block, Burst no Tuning Protection Array Matrix T = Top Boot B = Bottom Boot Speed 45 = 45ns 55 = 55ns 60 = 60ns Package T = PQFP80 ZA = LBGA80: 1.0mm pitch Temperature Range 3 = -40 to 125 C 6 = -40 to 85 C Option T = Tape & Reel Packing M58BW032B T 45 T 3 T
Note: Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
APPENDIX A. FLOW CHARTS
Figure 20. Program Flowchart and Pseudo Code
Start
Write 40h
Write Address & Data
Program Command: - write 40h, Address AAh - write Address & Data (memory enters read status state after the Program command)
Read Status Register
do: - read status register (E or G must be toggled) NO
b7 = 1 YES b3 = 0 YES b4 = 0 YES b1 = 0 YES End
while b7 = 1
NO
VPEN Invalid Error (1)
If b3 = 1, VPEN invalid error: - error handler
NO
Program Error (1)
If b4 = 1, Program error: - error handler
NO
Program to Protect Block Error
If b1 = 1, Program to Protected Block Error: - error handler
AI03850d
Note: 1. If an error is found, the Status Register must be cleared before further P/E operations.
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 21. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend Command: - write B0h - write 70h do: - read status register
Read Status Register
b7 = 1 YES b2 = 1 YES Write FFh
NO
while b7 = 1
NO
Program Complete
If b2 = 0, Program completed
Read Memory Array Command: - write FFh - one or more data reads from other blocks
Read data from another block
Write D0h
Write FFh
Program Continues
Read Data
Program Erase Resume Command: - write D0h to resume programming - if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase Suspend command was not issued).
AI00612b
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Figure 22. Block Erase Flowchart and Pseudo Code
Start
Write 20h
Write Block Address & D0h
Erase Command: - write 20h, Address 55h - write Block Address (A11-A19) & D0h (memory enters read status state after the Erase command)
Read Status Register
NO Suspend
YES
do: - read status register (E or G must be toggled) if Erase command given execute suspend erase loop while b7 = 1
b7 = 1
NO
Suspend Loop
YES b3 = 0 YES b4 and b5 =1 NO b5 = 0 YES b1 = 0 YES End
AI08623c
NO
VPEN Invalid Error (1)
If b3 = 1, VPEN invalid error: - error handler
YES
Command Sequence Error
If b4, b5 = 1, Command Sequence error: - error handler
NO
Erase Error (1)
If b5 = 1, Erase error: - error handler
NO
Erase to Protected Block Error
If b1 = 1, Erase to Protected Block Error: - error handler
Note: 1. If an error is found, the Status Register must be cleared before further P/E operations.
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend Command: - write B0h - write 70h do: - read status register
Read Status Register
b7 = 1 YES b6 = 1 YES Write FFh
NO
while b7 = 1
NO
Erase Complete
If b6 = 0, Erase completed
Read Memory Array command: - write FFh - one or more data reads from other blocks
Read data from another block or Program
Write D0h
Write FFh
Erase Continues
Read Data
Program/Erase Resume command: - write D0h to resume the Erase operation - if the Erase operation completed then this is not necessary. The device returns to Read mode as normal (as if the Program/Erase suspend was not issued).
AI00615b
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M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 24. Unlock Device and Change Tuning Protection Code Flowchart
Reset Add: don't care Data: FFh TUNING PROTECTION UNLOCK SEQUENCE Issue Read command 5th: Write Cycle
Device locked by tuning code
Add: don't care Data: 78h
1st: Write Cycle
Add: AAh Data: 48h
6th: Write Cycle
Add: 00000h Data: First 32 bit
2nd: Write Cycle (old code, factory setup = FFFFh)
Add: 00000h Data: First 32 bit
7th: Write Cycle (new code)
Add: don't care Data: FFh Issue Read command
b7 = 1 YES Add: don't care Data: 78h 3rd: Write Cycle
b7 = 1 YES Add: AAh Data: 48h 8th: Write Cycle
Add: 00001h Data: Second 32 bit
4th: Write Cycle (old code, factory setup = FFFFh)
Add: 00001h Data: Second 32 bit
9th: Write Cycle (new code)
b7 = 1 YES Read Status Register
b7 = 1 YES Reset
NO DEVICE LOCKED
b0 = 1 YES DEVICE UNLOCKED
Device locked by new code
AI04501b
50/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 25. Unlock Device and Program a Tuning Protected Block Flowchart
Reset Add: don't care Data: FFh TUNING PROTECTION UNLOCK SEQUENCE Issue Read command 5th: Write Cycle
Device locked by tuning code
Add: don't care Data: 78h
1st: Write Cycle
Add: AAh Data: 40h
6th: Write Cycle
Add: 00000h Data: First 32 bit
2nd: Write Cycle (First part of the tuning code)
Add: location to prog. 7th: Write Cycle Data: data to prog.
Add: don't care Data: FFh Issue Read command
b7 = 1 YES Add: don't care Data: 78h 3rd: Write Cycle
b7 = 1 YES Status Register check
Add: 00001h Data: Second 32 bit
4th: Write Cycle (Second part of the tuning code)
Location programmed
b7 = 1 YES Read Status Register
NO DEVICE LOCKED
b0 = 1 YES DEVICE UNLOCKED
AI04502b
51/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 26. Unlock Device and Erase a Tuning Protected Block Flowchart
Reset Add: don't care Data: FFh TUNING PROTECTION UNLOCK SEQUENCE Issue Read command 5th: Write Cycle
Device locked by tuning code
Add: don't care Data: 78h
1st: Write Cycle
Add: 55h Data: 20h
6th: Write Cycle
Add: 00000h Data: First 32 bit
2nd: Write Cycle (First part of the tuning code)
Add: block to erase Data: D0h
7th: Write Cycle
Add: don't care Data: FFh Issue Read command
b7 = 1 YES Add: don't care Data: 78h 3rd: Write Cycle
b7 = 1 YES Status Register check
Add: 00001h Data: Second 32 bit
4th: Write Cycle (Second part of the tuning code)
Block Erased
b7 = 1 YES Read Status Register
NO DEVICE LOCKED
b0 = 1 YES DEVICE UNLOCKED
AI04503b
52/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 27. Power-up Sequence to Burst the Flash
Power-up or Reset
Asynchronous Read
BCR bit 15 = '1'
Write 60h command
Set Burst Configuration Register Command: - write 60h - write 03h and BCR on A15-A0
Write 03h with A15-A0 BCR inputs
Synchronous Read
BCR bit 15 = '0' BCR bit 14-bit 0 = '1'
AI03834
53/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 28. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR COMMAND WRITE
90h YES READ ELEC. SIGNATURE
NO
READ ARRAY
98h YES READ CFI
NO D
70h YES READ STATUS
NO
20h YES ERASE SET-UP
NO
40h YES
NO
ERASE COMMAND ERROR
NO
D0h YES A
PROGRAM SET-UP
50h YES
NO E
C
CLEAR STATUS
D
READ STATUS
B
AI03835
54/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 29. Command Interface and Program Erase Controller Flowchart (b)
E
48h YES TP PROGRAM SET_UP
NO
78h YES
NO
F
TP UNLOCK SET_UP
60h YES
NO
FFh G SET BCR SET_UP YES
NO
03h YES
NO
D
AI03836
55/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 30. Command Interface and Program Erase Controller Flowchart (c)
B
A
ERASE YES READY NO NO READ STATUS
B0h YES
ERASE SUSPEND
YES
READY NO
NO
ERASE SUSPENDED YES
READ STATUS
READ STATUS
YES
70h NO YES PROGRAM SET_UP C YES READ STATUS
40h NO READ ARRAY NO
D0h
AI03837
56/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 31. Command Interface and Program Erase Controller Flowchart (d)
B
C
PROGRAM
YES
READY NO NO READ STATUS
B0h YES
PROGRAM SUSPEND
YES
READY NO
NO
PROGRAM SUSPENDED YES
READ STATUS
READ STATUS
YES
70h NO
READ ARRAY
NO
D0h
YES
READ STATUS
AI03838
57/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Figure 32. Command Interface and Program Erase Controller Flowchart (e)
B
F
TP PROGRAM
YES
READY
NO
READ STATUS
B
G
TP UNLOCK
YES
READY
NO
READ STATUS
AI03839
58/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
REVISION HISTORY
Table 25. Document Revision History
Date 20-Oct-2003 21-Oct-2003 Version 1.0 1.1 First Issue. Figure 7, AC Measurement Load Circuit modified. IDDB test condition updated in Table 5, DC Characteristics. Bit M3 no longer reserved, described in Burst Configuration Register section. Minor text changes. Program and Erase Suspend Latency Times added to Table Table 10., Program, Erase Times and Program Erase Endurance Cycles. A19 added in Figure 4.PQFP Connections (Top view through package). Table 6.Burst Configuration Register, Note 1 updated. DQ8-DQ15 and R signal names updated in Table 1., Signal Names. Description of Valid Data Ready (R).signal updated. Burst Length Bit (M2-M0).paragraph updated in Burst Configuration Register section. X-Latency of 8 clock cycles added in Table 6., Burst Configuration Register COMMAND INTERFACE section: Erase All Main Blocks command added, Read Electronic Signature Command, Read Status Register Command, Write to Buffer and Program Command, Set Block Protection Configuration Register Command and Clear Block Protection Configuration Register Command. updated. Erase All Main Blocks command added, Write to Buffer and Program, Set Burst Configuration Register, Set and Clear Block Protection commands updated in Table 8., Commands. Standby Status removed from Table 9., Read Electronic Signature. Definition of bit 4 updated in STATUS REGISTER section. tQVKH removed from Figure 13., Synchronous Burst Read (Data Valid from 'n' Clock Rising Edge). Datasheet status changed to Preliminary Data. Revision Details
20-Nov-2003
1.2
27-Apr-2004
2.0
30-July-2004
3.0
05-Nov-2004
4.0
59/60
M58BW032BT, M58BW032BB, M58BW032DT, M58BW032DB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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